1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device having field effect transistors functioned for converting a change in charge amount into an electric current.
2. Description of the Related Art
A non-volatile memory is known as one form of the conventional semiconductor memory device where one field effect transistor saves two bits of data (for example, as disclosed in Japanese Patent No. 2001-512290, equivalent to International Publication No. WO99/07000, referred to as Citation 1). Such a non-volatile memory will be described about the structure and the programming action.
The non-volatile memory of Citation 1 includes, as shown in FIG. 15, a gate electrode 909 provided via a gate insulating film on a P type well region 901 and a pair of N type diffusion areas 902 and 903 provided on the surface of the P type well region 901. The gate insulating film comprises so-called an ONO film (silicon oxide film/silicon nitride film/silicon oxide film) where a silicon nitride film 906 is sandwiched between two silicon oxide films 904 and 905. The silicon nitride film 906 includes memory regions 907 and 908 located close to ends of the two N type diffusion areas 902 and 903 respectively. In each of the memory regions 907 and 908, a two-bit data can be stored in one transistor by reading the drain current of a transistor from the quantity of charges.
The programming action on the non-volatile memory will now be described. The programming action involves injecting electrons into the memory regions 907 and 908. The action in Citation 1 is disclosed where the diffusion area 903 is supplied with 5.5 V and the gate electrode 909 is supplied with 10 V for injecting electrons into the memory region 908 at the right. For injecting electrons into the memory region 907 at the left, the diffusion area 902 is supplied with 5.5 V and the gate electrode 909 is supplied with 10 V. This allows each of the two memory regions 907 and 908 to be written down with a data. The other action is also disclosed for erasing or reading out a data on one of the two memory regions 907 and 908. Using those actions, the memory of two-bit data is feasible.
The gate insulating film in the non-volatile memory is arranged of the ONO, three-film, structure for driving the transistor and functioning as a memory film to save a charge. Accordingly, the non-volatile memory of Citation 1 is disadvantageous in the down sizing because its gate insulating film is hardly decreased in the thickness. Also, when the channel is shortened in the non-volatile memory, the two memory regions 907 and 908 of the transistor may interfere each other thus to interrupt the two-bit memory. Therefore, the down sizing of the non-volatile memory will fairly be restrictive.
Another semiconductor memory device is known which is capable of conducting the two-bit or more-bit memory with the use of one transistor and easily feasible of the down sizing (as disclosed, e.g., in Japanese Patent Laid-open Publication No. 2004-186663 (referred to as Citation 2)).
The fundamental structure as a memory device of the conventional semiconductor memory device will be described referring to FIGS. 16 and 17.
FIG. 16 is a schematic cross sectional view showing the memory device of Citation 2. As apparent from FIG. 16, the memory device includes a non-volatile memory cell which includes a gate electrode 13 having a gate length equal to that of a common transistor and provided via a gate insulating film 12 over an active region 11 of the first conduction type (e.g., one of P type and N type) formed on a part of a semiconductor substrate surface and a pair of charge retention sections 10A and 10B of a side wall spacer form provided on both sides of the gate electrode 13 and the gate insulating film 12 for memory of two-bit data. In other words, the charge retention section 10A is located on one side wall of the gate insulating film 12 and the gate electrode 13 while the other charge retention section 10B is located on the other side wall.
Two diffusion areas 17 and 18 of the second conduction type (e.g., the other of P type and N type) are provided at both sides of and beneath the charge retention sections 10A and 10B in the active region 11. The diffusion areas 17 and 18 (source/drain regions) are located as offset from the lowermost of the gate electrode 13 (from both ends of a channel region 41 provided beneath the gate electrode 13). Accordingly, in the active region 11, offset regions 42 are formed between the lowermost of the gate electrode 13 and the two diffusion areas 17 and 18 respectively.
As the charge retention sections 10A and 10B in the memory device are arranged independently of the gate insulating film 12, their memory function is isolated from the transistor function of the gate insulating film 12. Also, the charge retention sections 10A and 10B are separated from each other by the gate electrode 13, they can effectively be inhibited from interfering each other during the re-programming action. As the result, the memory device is capable of storing a two-bit or more-bit data and easily feasible of the down sizing.
Since the diffusion areas 17 and 18 are offset from the lowermost of the gate electrode 13, the inversion of the offset regions 42 beneath the charge retention sections 10A and 10B (at locations in the active region 11 opposite to the charge retention sections 10A and 10B) can be accelerated by the charge saved in the charge retention sections 10A and 10B, thus increasing the memory effect when the gate electrode 13 is supplied with a voltage. The memory effect indicates that the quantity of a change saved in the charge retention films (in the charge retention sections 10A and 10B) determines a change in the current flowing from one of the two diffusion areas to the other across the channel region 41 when the gate electrode 13 is supplied with a voltage. The higher the memory effect, the greater a change in the current will be increased.
As the diffusion areas 17 and 18 are offset from the gate electrode 13, the short channel effect will significantly be avoided as compared with a traditional logic transistor, hence decreasing the gate length to a shorter distance. Also, the structure suited for minimizing the short channel effect can employ the gate insulating film of a thickness greater than that of a logic transistor, hence improving the operational reliability.
FIG. 17 illustrates another example of the semiconductor memory device of Citation 2. In particular, each of the charge retention sections 10A and 10B shown in FIG. 16 comprises a silicon nitride film 15 as the second insulating film of a side wall shape and a silicon oxide film 14 as the first insulating film which isolates the silicon nitride film 15 from the gate electrode 13, the active region 11, and the diffusion areas 17 and 18. The silicon nitride film 15 has a function of retaining a charge (electrons or holes) while the silicon oxide film 14 has a function of inhibiting the leakage of a charge from the silicon nitride film 15.
More specifically, as shown in FIG. 17, the semiconductor memory device of Citation 2 comprises the action region of the first conduction type (e.g., one of P type or N type) formed on a part of a semiconductor substrate surface, the gate insulating film 12 provided on the action region, the gate electrode 13 provided on the gate insulating film 12, the charge retention sections 10A and 10B provided separately at both sides of the gate electrode 13, the diffusion areas 17 and 18 of the second conduction type (the other of P type and N type) provided separately beneath the charge retention sections 10A and 10B in the active region, and the channel region provided beneath the gate insulating film 12. In response to the quantity of charge saved therein, the charge retention sections 10A and 10B modifies the current which flows from one of the two diffusion areas 17 and 18 to the other across the channel region when the gate electrode 13 is supplied with a voltage. The charge retention sections 10A and 10B are arranged in which electrons or holes are injected and discharged for the memory of data.
The semiconductor memory device of Citation 2 serves as a memory device for converting a change in the charge saved in the charge retention sections 10A and 10B into an electric current. Since the two charge retention sections 10A and 10B provided at both sides of the gate electrode 13 are separated from the gate insulating film 12, their memory function is isolated from the transistor function of the gate insulating film 12. Accordingly, the gate insulating film 12 can be decreased in the thickness without interrupting the memory function, thus readily minimizing the short channel effect.
Also, since the two charge retention sections 10A and 10B provided at both sides of the gate electrode 13 are separated from each other by the gate electrode 13, they can effectively be prevented from being interfered by each other during the re-programming action. In other words, the distance between the two charge retention sections 10A and 10B is minimized. This allows the semiconductor memory device to store two-bit or more-bit data with the use of one transistor while being easily feasible of the down sizing.
However, the semiconductor memory device (non-volatile memory) of Citation 2 conducts the re-programming action with the lowermost (at both left and right sides) of its gate electrode supplied with an electric field during the memory action. If the first insulating film beneath the gate electrode fails to be uniform in the thickness, its thinner region may abruptly be intensified by the electric field. As the result, the first insulating film will be fractured thus causing the leakage of current.
For example, the silicon oxide film as the first insulating film is provided through reaction of silicon with specific gas (e.g., oxygen gas). When the supply of the gas is varied more or less, the resultant silicon oxide film may hardly be uniform in the thickness. Generally, the silicon oxide film is provided when the gate electrode has been deposited in the non-volatile memory. The supply of the gas may often be interrupted by the gate electrode and thus unstable at the lowermost of the gate electrode, hence resulting in a non-uniform thickness of the silicon oxide film.
FIGS. 18 and 19 are cross sectional views showing steps of a conventional method of manufacturing the semiconductor memory device. FIG. 20 is an enlarged view of FIG. 18c. As apparent from FIGS. 18b and 20, the semiconductor memory device manufactured by the conventional method has the opening provided at the bottom flush with the interface between the active region 11 and the gate insulating film 12. This prevents the thickness of the first insulating film 14 (of, e.g., silicon oxide) from being uniform particularly at both sides of the gate insulating film 12.
As disclosed, the charge retention sections in the semiconductor memory device of Citation 2 are located partially lower than the interface between the gate insulating film and the channel region. Since the charge retention sections in the semiconductor memory device are located partially lower than the interface between the gate insulating film and the channel region, they stay in the direction of propagation of the high energy charge during the programming action. Accordingly, the efficiency of injecting the charge into the charge retention sections can be improved, thus increasing the speed of the programming action. Simultaneously, the current during the programming action can be reduced. In the latter case, the power consumption during the programming action will thus be lowered. In more detail, the bottom of the opening is located at a distance of preferably 2 nm to 15 nm from the interface. The deeper the opening, the supply of the gas will increase. As the result, the silicon oxide film as the first insulating film can be uniform in the thickness. However, Citation 2 fails to disclose a method of manufacturing the semiconductor memory device which is capable of overcoming the drawbacks derived from the quality of the silicon oxide film. It is hence desired to invent a novel method of manufacturing the semiconductor memory device of which the first insulating film is uniform in the thickness.